1. Technical Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly, to a charge pump circuit for improving switching characteristics and reducing leakage current and a phase locked loop having the same.
2. Description of Related Art
A phase locked loop (PLL) comprises a circuit for synchronizing the frequency of an output signal of a voltage controlled oscillator with the frequency of an input signal. PLLs are typically utilized for applications such as signal synchronization and frequency synthesization.
In general, a phase-locked loop comprises a phase detector, a charge pump circuit, a loop filter and a voltage controlled oscillator, which are connected in series. The phase detector monitors the difference in phase between an input signal and an output signal of the voltage controlled oscillator and then outputs either an up control signal or a down control signal to the loop filter based on the detected phase difference.
In particular, the loop filter, which typically comprises a capacitor with a large capacitance, charges the capacitor in response to the up control signal so that the output voltage of the loop filter increases. When the output voltage of the loop filter increases, the frequency of the voltage controlled oscillator increases.
Also, the output voltage of the loop filter decreases when the capacitor discharges in response to the down control signal. The frequency of the voltage controlled oscillator decreases when the output voltage of the loop filter decreases.
In other words, if the up control signal is active (that is, logic xe2x80x98highxe2x80x99), the charge pump circuit supplies a charge current having a predetermined magnitude to the capacitor of the loop filter. If the down control signal is active, the charge pump circuit draws a discharge current having the same magnitude from the capacitor of the loop filter. In essence, the charge pump circuit is a circuit for controlling the output voltage of the loop filter.
To remove a dead zone in which the PLL cannot detect a minute phase difference, the up and down control signals become active simultaneously for a short time even in a locked state. At this time, the output voltage of the loop filter is maintained at a constant level (so as to stabilize the output frequency of the voltage controlled oscillator) only if the amount of the charge current flowing to the loop filter is exactly the same as that of the discharge current flowing from the loop filter.
However, if there is a difference in phase between the charge current and the discharge current, spurious signals appear in the spectrum of the output signal of the voltage controlled oscillator. To equalize the charge current and the discharge current of the loop filter, their normal states and switching characteristics responding to the up and down control signals are made to be identical with each other.
Also, if the up and down control signals become inactive, the output impedance of the charge pump circuit approaches infinity. Then, only if the amount of leakage current flowing to/from the loop filter is very little, the output voltage of the loop filter is maintained at a constant level.
FIG. 1 is a circuit diagram illustrating a conventional drain-switched charge pump circuit 10. Referring to FIG. 1, the drain-switched charge pump circuit 10 includes a first reference current source 11, a first current mirror circuit 15 having PMOS transistors P1 and P2 and a first capacitor C1, a first switching transistor P3 responsive to an up control signal UP, a second reference current source 13, a second current mirror circuit 17 having NMOS transistors N1 and N2 and a second capacitor C2, and a second switching transistor N3 responsive to a down control signal DN.
Assume that the PMOS transistors P1 and P2 have the same aspect ratio (i.e., the ratio of the width of a channel to the length of the channel) and that the first switching transistor P3 is turned on, the first reference current up REF (i.e., charge current) flows into the drain of the first switching transistor P3. Further, assuming that the NMOS transistors N1 and N2 have the same aspect ratio and that the second switching transistor N3 is turned on, the second reference current IDN,REF (i.e., discharge current) flows to ground Vss through the drain of the second switching transistor N3.
The moment the first and second switching transistor P3 and N3 of the drain-switched charge pump circuit 10 are turned on or turned off, a peak current is generated due to difference in drain-source voltage between the transistors P2 and N2 connected in series and the first and second switching transistors P3 and N3. Consequently, at the moment of switching, the matching characteristics of the charge current IUP,REF and the discharge current IDN,REF are extremely poor.
FIG. 2 is a circuit diagram illustrating a conventional gate-switched charge pump circuit 20. Referring to FIG. 2, the gate-switched charge pump circuit 20 includes a first reference current source 21, a charge unit 25 having a first capacitor C3 and PMOS transistors P21, P22, P23, and P24, a second reference current source 23, and a discharge unit 27 having a second capacitor C4 and NMOS transistors N21, N22, N23 and N24.
The charge unit 25 includes a charging transistor P22, a first switching transistor P23 for switching the charging transistor P22, and a second switching transistor P24, which reduces the switching load of the PMOS transistor P21 and complementarily switches with the first switching transistor P23. Thus, in the case of switching with the second switching transistor P24, the voltage of the source of the second switching transistor P24 is not changed.
The discharge unit 27 includes the discharging transistor N22, the third switching transistor N23 for switching the discharging transistor N22, and the fourth switching transistor N24, which reduces the switching load of the NMOS transistor N21 and complementarily switches with the third switching transistor N23. Thus, in the case of switching with the fourth switching transistor N24, the voltage of the drain of the fourth switching transistor N24 is not changed.
One problem associated with the conventional gate-switched charge pump circuit 20 is that switching transistors P23, P24, N23 and N24, which generate and respectively respond to an UP control signal, an inverted UP control signal, a DN control signal and an inverted DN control signal, must be realized in the gate switched charge pump circuit 20.
Moreover, when the switching transistors P23 and P24 are switched, there exists a period during which they are simultaneously turned on. Accordingly, electric charge stored in the capacitor C3 is discharged into power supply voltage Vdd. Similarly, when the transistors N23 and N24 are switched, there also exists a period during which they are simultaneously turned on. At this time, electric charge stored in the capacitor C4 is discharged into the ground voltage Vss.
The source voltage of the switching transistor P24 and the drain voltage of the switching transistor N24 are not maintained at a constant level and thus before and after switching, the first reference current IUP,REF and the second reference current IDN,REF are not exactly mirrored to the charge current and the discharge current, respectively. Thus, the matching characteristics of the charge current and the discharge current are extremely poor.
FIG. 3 is a circuit diagram illustrating a conventional source-switched charge pump circuit 30. In FIG. 3, the source-switched charge pump circuit 30 includes a first reference current source 31, a first current mirroring circuit consisting of PMOS transistors P31 and P32, a first switching transistor P33, a first matching transistor P34 for matching voltage drops occurring in the first switching transistor P33. The circuit 30 further includes a second reference current source 33, a second current mirroring circuit consisting of NMOS transistors N31 and N32, a second switching transistor N33 and a second matching transistor N34 for matching voltage drops occurring in the second switching transistor N33.
In a case where an up control signal UP becomes active and then the first switching transistor P33 is turned on, node xe2x80x9caxe2x80x9d is quickly charged to the power supply voltage Vdd. However, in a case where the first switching transistor P33 is turned off, the path for charging node xe2x80x9caxe2x80x9d is disconnected. Also, in a case where a down control signal DN becomes active and then the second switching transistor N33 is turned on, node xe2x80x9cbxe2x80x9d is quickly discharged to the ground voltage Vss. However if the second switching transistor P33 is turned off, the path for discharging node xe2x80x9cbxe2x80x9d is disconnected. Consequently, switching is performed very slowly thereby deteriorating the matching characteristics of the charge current IUP,REF and the discharge current IDN,REF.
In a state in which the charge pump circuits 10, 20 and 30 illustrated in FIGS. 1, 2 and 3, respectively, are turned off, output transistors P2, N2, P22, N22, P32 and N32 have a gate-source voltage of 0V which is not less than the threshold voltage. Therefore, when an up control signal and a down control signal are inactive (that is, logic xe2x80x98lowxe2x80x99), leakage current flows. Particularly, as the operational temperature of a charge pump increases, the leakage current increases exponentially, thereby negatively affecting the operation of a phase locked loop (PLL).
To solve the above problems, it is an object of the present invention to provide a charge pump circuit that is capable of improving the matching and switching characteristics of charge current and discharge current and reducing leakage current, and to provide a phase locked loop comprising the charge pump circuit.
According to one embodiment of the present invention, a charge pump circuit comprises a first current source, a first switching device, and a pull-down device. The first current source sources current to an output terminal of the charge pump circuit in response to a first bias voltage. The first switching device is connected between a first power supply and the first current source and is switched in response to a first control signal, and the pull-down device pulls down the voltage of a connection node between the first current source and the first switching device.
The charge pump circuit further comprises a second current source, a second switching device, and a pull-up device. The second current source sinks current from an output terminal of the charge pump circuit in response to a second bias voltage. The second switching device is connected between a second power supply and the second current source and is switched in response to a second control signal, and the pull-up device pulls up the voltage of a connection node between the second current source and the second switching device. The charge pump circuit further comprise a first bias circuit for generating the first bias voltage and a second bias circuit for generating the second bias voltage.
According to another embodiment of the present invention, a charge pump circuit comprises a first current source, a second current source, a first switching device, a first pull-down device, and a second pull-down device. The first current source sources current to a first node in response to a first bias voltage. The second current source is connected between the first node and an output terminal of the charge pump circuit and sources current to the output terminal of the charge pump circuit in response to a second bias voltage. The first switching device is connected between a first power supply and the first current source and is switched in response to a first control signal. The first pull-down device pulls down the voltage of a connection node between the first current source and the first switching device in response to the first control signal, and the second pull-down device pulls down the voltage of the first node in response to the first control signal.
The charge pump circuit further comprise a third current source, a fourth current source, a second switching device, a first pull-up device, and a second pull-up device. The third current source sinks current from a second node in response to a third bias voltage. The fourth current source is connected between the third current source and the output terminal of the charge pump circuit and sinks current from the output terminal of the charge pump circuit in response to a fourth bias voltage. The second switching device is connected between the third current source and a second power supply and is switched in response to a second control signal. The first pull-up device pulls up the voltage of a connection node between the third current source and the second switching device in response to the second control signal, and the second pull-up device pulls up the voltage of the second node in response to the second control signal.
According to another embodiment of the present invention, a phase locked loop comprises a loop filter, a voltage-controlled oscillator, a phase detector and a charge pump circuit. The voltage-controlled oscillator outputs an internal signal in response to an output signal of the loop filter. The phase detector detects a difference in phase between a reference signal and the internal signal and outputs a first control signal or a second control signal. The charge pump circuit, which is operatively connected between the phase detector and the loop filter, controls the output voltage of the loop filter in response to the first control signal or the second control signal. The charge pump circuit comprises an architecture of a charge pump circuit according any one of the embodiments of the present invention.